Charge loss failure mitigation

ABSTRACT

Methods of operating a memory include reading a particular grouping of memory cells using a read voltage having a particular voltage level, determining a number of memory cells of a subset of memory cells of the particular grouping of memory cells having a particular data state, and, if the number of memory cells of the subset of memory cells having the particular data state is less than a particular threshold, adjusting a voltage level of the read voltage in response to the number of memory cells of the subset of memory cells having the particular data state and reading the particular grouping of memory cells using the read voltage having the adjusted voltage level.

RELATED APPLICATION

This Application is a Continuation of U.S. application Ser. No.15/856,132, titled “CHARGE LOSS FAILURE MITIGATION,” filed Dec. 28,2017, issued as U.S. Pat. No. 10,242,747 on Mar. 26, 2019, which iscommonly assigned and incorporated herein by reference.

TECHNICAL FIELD

The present disclosure relates generally to memory and, in particular,in one or more embodiments, the present disclosure relates to methods ofoperating memory for mitigating charge loss failure.

BACKGROUND

Integrated circuit devices traverse a broad range of electronic devices.One particular type include memory devices, oftentimes referred tosimply as memory. Memory devices are typically provided as internal,semiconductor, integrated circuit devices in computers or otherelectronic devices. There are many different types of memory includingrandom-access memory (RAM), read only memory (ROM), dynamic randomaccess memory (DRAM), synchronous dynamic random access memory (SDRAM),and flash memory.

Flash memory has developed into a popular source of non-volatile memoryfor a wide range of electronic applications. Flash memory typically usea one-transistor memory cell that allows for high memory densities, highreliability, and low power consumption. Changes in threshold voltage(Vt) of the memory cells, through programming (which is often referredto as writing) of charge storage structures (e.g., floating gates orcharge traps) or other physical phenomena (e.g., phase change orpolarization), determine the data state (e.g., data value) of eachmemory cell. Common uses for flash memory and other non-volatile memoryinclude personal computers, personal digital assistants (PDAs), digitalcameras, digital media players, digital recorders, games, appliances,vehicles, wireless devices, mobile telephones, and removable memorymodules, and the uses for non-volatile memory continue to expand.

A NAND flash memory is a common type of flash memory device, so calledfor the logical form in which the basic memory cell configuration isarranged. Typically, the array of memory cells for NAND flash memory isarranged such that the control gate of each memory cell of a row of thearray is connected together to form an access line, such as a word line.Columns of the array include strings (often termed NAND strings) ofmemory cells connected together in series between a pair of selectgates, e.g., a source select transistor and a drain select transistor.Each source select transistor may be connected to a source, while eachdrain select transistor may be connected to a data line, such as columnbit line. Variations using more than one select gate between a string ofmemory cells and the source, and/or between the string of memory cellsand the data line, are known.

In programming memory, memory cells may generally be programmed as whatare often termed single-level cells (SLC) or multiple-level cells (MLC).SLC may use a single memory cell to represent one digit (e.g., bit) ofdata. For example, in SLC, a Vt of 2.5V might indicate a programmedmemory cell (e.g., representing a logical 0) while a Vt of −0.5V mightindicate an erased cell (e.g., representing a logical 1). An MLC usesmore than two Vt ranges, where each Vt range indicates a different datastate. Multiple-level cells can take advantage of the analog nature of atraditional charge storage cell by assigning a bit pattern to a specificVt range. While MLC typically uses a memory cell to represent one datastate of a binary number of data states (e.g., 4, 8, 16, . . . ), amemory cell operated as MLC may be used to represent a non-binary numberof data states. For example, where the MLC uses three Vt ranges, twomemory cells might be used to collectively represent one of eight datastates.

In some cases, memory cells of a memory might be pre-programmed withdata prior to connecting that memory to other circuitry. Connecting amemory to other circuitry may cause thermal stress to the memory. Forexample, where reflow soldering techniques are used to connect a memoryto a circuit board, the circuit board and memory would generally besubjected to high levels of heat in order to melt, i.e., reflow, thesolder joints to make the desired connections. Thermal stress may causechanges in the threshold voltages of the pre-programmed memory cellsthrough charge loss, which may result in shifting and/or widening of thethreshold voltage distributions of the memory cells representing thevarious data states. Similarly, extended use of a memory might alsoresult in charge loss. For example, memory is increasingly being used inembedded applications expected to exhibit usage life significantlylonger than a typical solid-state drive or mobile phone application,such as in the automotive industry where infotainment, instrumentcluster, engine control and driver assistance systems are increasinglyreliant on such memories. Where threshold voltage distributions shiftand/or widen too much, a memory cell may indicate a data state otherthan its intended data state. At some point, this charge loss can causeread errors for an end-user, and may ultimately cause a memory tobecome, or be deemed, unusable.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified block diagram of a memory in communication with aprocessor as part of an electronic system, according to an embodiment.

FIGS. 2A-2B are schematics of portions of an array of memory cells ascould be used in a memory of the type described with reference to FIG.1.

FIG. 3A illustrates an example of threshold voltage distributions for apopulation of single-level memory cells.

FIG. 3B illustrates an example of threshold voltage distributions for apopulation of multi-level memory cells.

FIGS. 4A-4B illustrate examples of data structures that might be usedwith embodiments.

FIGS. 5A-5D depict flowcharts of methods of operating a memory inaccordance with embodiments.

FIG. 6 illustrates adjustment of a read voltage level in accordance withan embodiment.

DETAILED DESCRIPTION

In the following detailed description, reference is made to theaccompanying drawings that form a part hereof, and in which is shown, byway of illustration, specific embodiments. In the drawings, likereference numerals describe substantially similar components throughoutthe several views. Other embodiments may be utilized and structural,logical and electrical changes may be made without departing from thescope of the present disclosure. The following detailed description is,therefore, not to be taken in a limiting sense.

The term “semiconductor” used herein can refer to, for example, a layerof material, a wafer, or a substrate, and includes any basesemiconductor structure. “Semiconductor” is to be understood asincluding silicon-on-sapphire (SOS) technology, silicon-on-insulator(SOI) technology, thin film transistor (TFT) technology, doped andundoped semiconductors, epitaxial layers of a silicon supported by abase semiconductor structure, as well as other semiconductor structureswell known to one skilled in the art. Furthermore, when reference ismade to a semiconductor in the following description, previous processsteps may have been utilized to form regions/junctions in the basesemiconductor structure, and the term semiconductor can include theunderlying layers containing such regions/junctions.

The term “conductive” as used herein, as well as its various relatedforms, e.g., conduct, conductively, conducting, conduction,conductivity, etc., refers to electrically conductive unless otherwiseapparent from the context. Similarly, the term “connecting” as usedherein, as well as its various related forms, e.g., connect, connected,connection, etc., refers to electrically connecting unless otherwiseapparent from the context.

FIG. 1 is a simplified block diagram of a first apparatus (e.g., anintegrated circuit device), in the form of a memory (e.g., memorydevice) 100, in communication with a second apparatus, in the form of aprocessor 130, as part of a third apparatus, in the form of anelectronic system, according to an embodiment. Some examples ofelectronic systems include personal computers, personal digitalassistants (PDAs), digital cameras, digital media players, digitalrecorders, games, appliances, vehicles, wireless devices, cellulartelephones and the like. The processor 130, e.g., a controller externalto the memory device 100, may be a memory controller or other externalhost device.

Memory device 100 includes an array of memory cells 104 logicallyarranged in rows and columns. Memory cells of a logical row aretypically connected to the same access line (commonly referred to as aword line) while memory cells of a logical column are typicallyselectively connected to the same data line (commonly referred to as abit line). A single access line may be associated with more than onelogical row of memory cells and a single data line may be associatedwith more than one logical column. Memory cells (not shown in FIG. 1) ofat least a portion of array of memory cells 104 are capable of beingprogrammed to one of at least two data states.

A row decode circuitry 108 and a column decode circuitry 110 areprovided to decode address signals. Address signals are received anddecoded to access the array of memory cells 104. Memory device 100 alsoincludes input/output (I/O) control circuitry 112 to manage input ofcommands, addresses and data to the memory device 100 as well as outputof data and status information from the memory device 100. An addressregister 114 is in communication with I/O control circuitry 112 and rowdecode circuitry 108 and column decode circuitry 110 to latch theaddress signals prior to decoding. A command register 124 is incommunication with I/O control circuitry 112 and control logic 116 tolatch incoming commands. A trim register 128 may be in communicationwith the control logic 116 to store trim settings. Although depicted asa separate storage register, trim register 128 may represent a portionof the array of memory cells 104. Trim settings are generally valuesused by an integrated circuit device to define values of voltage levels,control signals, timing parameters, quantities, options, etc. to be usedduring operation of that integrated circuit device.

A controller (e.g., the control logic 116 internal to the memory device100) controls access to the array of memory cells 104 in response to thecommands and generates status information for the external processor130, i.e., control logic 116 is configured to perform access operations(e.g., read operations, program operations and/or erase operations) andother operations in accordance with embodiments described herein. Thecontrol logic 116 is in communication with row decode circuitry 108 andcolumn decode circuitry 110 to control the row decode circuitry 108 andcolumn decode circuitry 110 in response to the addresses.

Control logic 116 may also be in communication with a cache register118. Cache register 118 may latch data, either incoming or outgoing, asdirected by control logic 116 to temporarily store data while the arrayof memory cells 104 is busy writing or reading, respectively, otherdata. During a program operation (e.g., write operation), data may bepassed from the cache register 118 to data register 120 for transfer tothe array of memory cells 104; then new data may be latched in the cacheregister 118 from the I/O control circuitry 112. During a readoperation, data may be passed from the cache register 118 to the I/Ocontrol circuitry 112 for output to the external processor 130; then newdata may be passed from the data register 120 to the cache register 118.A status register 122 is in communication with I/O control circuitry 112and control logic 116 to latch the status information for output to theprocessor 130.

Memory device 100 receives control signals at control logic 116 fromprocessor 130 over a control link 132. The control signals might includea chip enable CE #, a command latch enable CLE, an address latch enableALE, a write enable WE #, a read enable RE #, and a write protect WP #.Additional or alternative control signals (not shown) may be furtherreceived over control link 132 depending upon the nature of the memorydevice 100. Memory device 100 receives command signals (which representcommands), address signals (which represent addresses), and data signals(which represent data) from processor 130 over a multiplexedinput/output (I/O) bus 134 and outputs data to processor 130 over I/Obus 134.

For example, the commands may be received over input/output (I/O) pins[7:0] of I/O bus 134 at I/O control circuitry 112 and may be writteninto command register 124. The addresses may be received overinput/output (I/O) pins [7:0] of I/O bus 134 at I/O control circuitry112 and may be written into address register 114. The data may bereceived over input/output (I/O) pins [7:0] for an 8-bit device orinput/output (I/O) pins [15:0] for a 16-bit device at I/O controlcircuitry 112 and may be written into cache register 118. The data maybe subsequently written into data register 120 for programming the arrayof memory cells 104. For another embodiment, cache register 118 may beomitted, and the data may be written directly into data register 120.Data may also be output over input/output (I/O) pins [7:0] for an 8-bitdevice or input/output (I/O) pins [15:0] for a 16-bit device. The I/Obus 134 might further include complementary data strobes DQS and DQSNthat may provide a synchronous reference for data input and output.Although reference may be made to I/O pins, they may include anyconductive node providing for electrical connection to the memory device100 by an external device (e.g., processor 130), such as conductive padsor conductive bumps as are commonly used.

It will be appreciated by those skilled in the art that additionalcircuitry and signals can be provided, and that the memory device 100 ofFIG. 1 has been simplified. It should be recognized that thefunctionality of the various block components described with referenceto FIG. 1 may not necessarily be segregated to distinct components orcomponent portions of an integrated circuit device. For example, asingle component or component portion of an integrated circuit devicecould be adapted to perform the functionality of more than one blockcomponent of FIG. 1. Alternatively, one or more components or componentportions of an integrated circuit device could be combined to performthe functionality of a single block component of FIG. 1.

Additionally, while specific I/O pins are described in accordance withpopular conventions for receipt and output of the various signals, it isnoted that other combinations or numbers of I/O pins may be used in thevarious embodiments.

FIG. 2A is a schematic of a portion of an array of memory cells 200A ascould be used in a memory of the type described with reference to FIG.1, e.g., as a portion of array of memory cells 104. Memory array 200Aincludes access lines, such as word lines 202 ₀ to 202 _(N), and datalines, such as bit lines 204 ₀ to 204 _(M). The word lines 202 may beconnected to global access lines (e.g., global word lines), not shown inFIG. 2A, in a many-to-one relationship. For some embodiments, memoryarray 200A may be formed over a semiconductor that, for example, may beconductively doped to have a conductivity type, such as a p-typeconductivity, e.g., to form a p-well, or an n-type conductivity, e.g.,to form an n-well.

Memory array 200A might be arranged in rows (each corresponding to aword line 202) and columns (each corresponding to a bit line 204). Eachcolumn may include a string of series-connected memory cells (e.g.,non-volatile memory cells), such as one of NAND strings 206 ₀ to 206_(M). Each NAND string 206 might be connected (e.g., selectivelyconnected) to a common source (SRC) 216 and might include memory cells208 ₀ to 208 _(N). The memory cells 208 may represent non-volatilememory cells for storage of data. The memory cells 208 of each NANDstring 206 might be connected in series between a select gate 210 (e.g.,a field-effect transistor), such as one of the select gates 210 ₀ to 210_(M) (e.g., that may be source select transistors, commonly referred toas select gate source), and a select gate 212 (e.g., a field-effecttransistor), such as one of the select gates 212 ₀ to 212 _(M) (e.g.,that may be drain select transistors, commonly referred to as selectgate drain). Select gates 210 ₀ to 210 _(M) might be commonly connectedto a select line 214, such as a source select line (SGS), and selectgates 212 ₀ to 212 _(M) might be commonly connected to a select line215, such as a drain select line (SGD). Although depicted as traditionalfield-effect transistors, the select gates 210 and 212 may utilize astructure similar to (e.g., the same as) the memory cells 208. Theselect gates 210 and 212 might represent a plurality of select gatesconnected in series, with each select gate in series configured toreceive a same or independent control signal.

A source of each select gate 210 might be connected to common source216. The drain of each select gate 210 might be connected to a memorycell 208 ₀ of the corresponding NAND string 206. For example, the drainof select gate 210 ₀ might be connected to memory cell 208 ₀ of thecorresponding NAND string 206 ₀. Therefore, each select gate 210 mightbe configured to selectively connect a corresponding NAND string 206 tocommon source 216. A control gate of each select gate 210 might beconnected to select line 214.

The drain of each select gate 212 might be connected to the bit line 204for the corresponding NAND string 206. For example, the drain of selectgate 212 ₀ might be connected to the bit line 204 ₀ for thecorresponding NAND string 206 ₀. The source of each select gate 212might be connected to a memory cell 208 _(N) of the corresponding NANDstring 206. For example, the source of select gate 212 ₀ might beconnected to memory cell 208 _(N) of the corresponding NAND string 206₀. Therefore, each select gate 212 might be configured to selectivelyconnect a corresponding NAND string 206 to the corresponding bit line204. A control gate of each select gate 212 might be connected to selectline 215.

The memory array in FIG. 2A might be a three-dimensional memory array,e.g., where NAND strings 206 may extend substantially perpendicular to aplane containing the common source 216 and to a plane containing aplurality of bit lines 204 that may be substantially parallel to theplane containing the common source 216.

Typical construction of memory cells 208 includes a data-storagestructure 234 (e.g., a floating gate, charge trap, etc.) that candetermine a data state of the memory cell (e.g., through changes inthreshold voltage), and a control gate 236, as shown in FIG. 2A. Thedata-storage structure 234 may include both conductive and dielectricstructures while the control gate 236 is generally formed of one or moreconductive materials. In some cases, memory cells 208 may further have adefined source/drain (e.g., source) 230 and a defined source/drain(e.g., drain) 232. Memory cells 208 have their control gates 236connected to (and in some cases form) a word line 202.

A column of the memory cells 208 may be a NAND string 206 or a pluralityof NAND strings 206 selectively connected to a given bit line 204. A rowof the memory cells 208 may be memory cells 208 commonly connected to agiven word line 202. A row of memory cells 208 can, but need not,include all memory cells 208 commonly connected to a given word line202. Rows of memory cells 208 may often be divided into one or moregroups of physical pages of memory cells 208, and physical pages ofmemory cells 208 often include every other memory cell 208 commonlyconnected to a given word line 202. For example, memory cells 208commonly connected to word line 202 _(N) and selectively connected toeven bit lines 204 (e.g., bit lines 204 ₀, 204 ₂, 204 ₄, etc.) may beone physical page of memory cells 208 (e.g., even memory cells) whilememory cells 208 commonly connected to word line 202 _(N) andselectively connected to odd bit lines 204 (e.g., bit lines 204 ₁, 204₃, 204 ₅, etc.) may be another physical page of memory cells 208 (e.g.,odd memory cells). Although bit lines 204 ₃-204 ₅ are not explicitlydepicted in FIG. 2A, it is apparent from the figure that the bit lines204 of the array of memory cells 200A may be numbered consecutively frombit line 204 ₀ to bit line 204 _(M). Other groupings of memory cells 208commonly connected to a given word line 202 may also define a physicalpage of memory cells 208. For certain memory devices, all memory cellscommonly connected to a given word line might be deemed a physical pageof memory cells. The portion of a physical page of memory cells (which,in some embodiments, could still be the entire row) that is read duringa single read operation or programmed during a single programmingoperation (e.g., an upper or lower page of memory cells) might be deemeda logical page of memory cells. A block of memory cells may includethose memory cells that are configured to be erased together, such asall memory cells connected to word lines 202 ₀-202 _(N) (e.g., all NANDstrings 206 sharing common word lines 202). Unless expresslydistinguished, a reference to a page of memory cells herein refers tothe memory cells of a logical page of memory cells.

FIG. 2B is another schematic of a portion of an array of memory cells200 _(B) as could be used in a memory of the type described withreference to FIG. 1, e.g., as a portion of array of memory cells 104.Like numbered elements in FIG. 2B correspond to the description asprovided with respect to FIG. 2A. FIG. 2B provides additional detail ofone example of a three-dimensional NAND memory array structure. Thethree-dimensional NAND memory array 200 _(B) may incorporate verticalstructures which may include semiconductor pillars where a portion of apillar may act as a channel region of the memory cells of NAND strings206. The NAND strings 206 may be each selectively connected to a bitline 204 ₀-204 _(M) by a select transistor 212 (e.g., that may be drainselect transistors, commonly referred to as select gate drain) and to acommon source 216 by a select transistor 210 (e.g., that may be sourceselect transistors, commonly referred to as select gate source).Multiple NAND strings 206 might be selectively connected to the same bitline 204. Subsets of NAND strings 206 can be connected to theirrespective bit lines 204 by biasing the select lines 215 ₀-215 _(K) toselectively activate particular select transistors 212 each between aNAND string 206 and a bit line 204. The select transistors 210 can beactivated by biasing the select line 214. Each word line 202 may beconnected to multiple rows of memory cells of the memory array 200 _(B).Rows of memory cells that are commonly connected to each other by aparticular word line 202 may collectively be referred to as tiers.

FIG. 3A illustrates an example of threshold voltage distributions for apopulation of one-bit SLC memory cells. Although typically referred toas single-level memory cells, such a memory cell might be programmed toa threshold voltage (Vt) that falls within one of two differentthreshold voltage distributions 301 or 302, each being used to representa data state corresponding to the one bit of data. The threshold voltagedistribution 301 typically has a greater width than the thresholdvoltage distribution 302 as memory cells are generally all placed in thedata state corresponding to the threshold voltage distribution 301, thena subset of those memory cells are subsequently programmed to have athreshold voltage in the threshold voltage distribution 302. Asprogramming operations are generally more incrementally controlled thanerase operations, the threshold voltage distribution 302 may tend tohave a tighter distribution. A dead space 303 (e.g., sometimes referredto as a margin, and might be 2V or greater) is typically maintainedbetween the adjacent threshold voltage distributions 301 and 302 to keepthe threshold voltage distributions from overlapping. As an example, ifthe threshold voltage of a memory cell is within the threshold voltagedistribution 301, the memory cell in this case is storing a logical ‘1’data state and is typically referred to as the erased state of thememory cell. If the threshold voltage is within the threshold voltagedistribution 302, the memory cell in this case is storing a logical ‘0’data state.

FIG. 3B illustrates an example of threshold voltage distributions for apopulation of a four-level (e.g., two-bit) MLC memory cells. Forexample, such a memory cell might be programmed to a threshold voltage(Vt) that falls within one of four different threshold voltagedistributions 304-307, each being used to represent a data statecorresponding to a bit pattern comprised of two bits. The thresholdvoltage distribution 304 typically has a greater width than theremaining threshold voltage distributions 305-307 as memory cells aregenerally all placed in the data state corresponding to the thresholdvoltage distribution 304, then subsets of those memory cells aresubsequently programmed to have threshold voltages in one of thethreshold voltage distributions 305-307. As programming operations aregenerally more incrementally controlled than erase operations, thesethreshold voltage distributions 305-307 may tend to have tighterdistributions.

The threshold voltage distributions 305-307 might each have a width 308,e.g., a width of 750 mV. In addition, a dead space 309 (e.g., sometimesreferred to as a margin, and might be approximately 500 mV or greater)is typically maintained between adjacent threshold voltage distributions304-307 to keep the threshold voltage distributions from overlapping. Asan example, if the threshold voltage of a memory cell is within thefirst of the four threshold voltage distributions 304, the memory cellin this case is storing a logical ‘11’ data state and is typicallyreferred to as the erased state of the memory cell. If the thresholdvoltage is within the second of the four threshold voltage distributions305, the memory cell in this case is storing a logical ‘10’ data state.A threshold voltage in the third threshold voltage distribution 306would indicate that the memory cell in this case is storing a logical‘00’ data state. Finally, a threshold voltage residing in the fourththreshold voltage distribution 307 indicates that a logical ‘01’ datastate is stored in the memory cell.

As previously noted, a portion of an array of memory cells of a memorymight be pre-programmed with data prior to connecting that memory toother circuitry, e.g., such as connecting the memory device 100 to theprocessor 130 as depicted in FIG. 1, or connecting the memory device 100to a circuit board (not shown). This data may be prone to experiencingcharge loss due to exposures to high levels of heat, such as experiencedduring reflow soldering techniques, or due to extended periods of usage,such as experienced in embedded systems designed for extended usagelife. Charge loss can cause read errors for an end-user.

One method used to improve reliability of such data is to utilize memorycells programmed as SLC memory cells, due to its generally larger deadspace relative to MLC memory cells. Another method used to improvereliability of such pre-programmed data is to utilize memory cellsprogrammed as MLC memory cells, but to utilize fewer than the intendednumber of data states for the memory cells storing that data. Forexample, memory cells of a four-level MLC such as described in FIG. 3Bmight be operated using a method of storage often referred to aspadding, which programs a memory cell to either the data statecorresponding to the threshold voltage distribution 304 corresponding tothe erased state to represent one data value (e.g., a logical ‘1’ datastate), or to the data state corresponding to the threshold voltagedistribution 307 (e.g., the highest threshold voltage distribution) torepresent a different data value (e.g., a logical ‘0’ data state). Suchpadding can provide further margin between data states than operatingthe memory cell as standard SLC.

Another technique used to improve reliability of such pre-programmeddata is to program multiple copies of data/data complement pairs. Forexample, a byte of data, e.g., 01100101, and its complement, e.g.,10011010 might both be programmed to a page of memory cells. Uponreading the page of memory cells, the data and its complement might besubjected to an XOR operation to determine whether each bit of the readdata byte is the complement of its corresponding bit of the read datacomplement byte. If the XOR operation confirms that each bit of the readdata byte is the complement of its corresponding bit of the read datacomplement byte, the data byte can be deemed to be valid. Otherwise itmight be deemed to be invalid. Multiple copies of such data/datacomplement pairs might be stored to the page of memory cells, or toadditional pages of memory cells, to increase the probability that avalid data/data complement pair can be found.

Despite using one or more of such techniques of improving reliability,charge loss may still result in a failure to identify valid data foreach byte of the pre-programmed data. Such pre-programmed data oftencontains initialization parameters for the memory, such as configurationdata, including voltage levels, control signals, timing parameters,quantities, options, etc. Where no valid copy of configuration data isidentified, the memory may be deemed to be unusable or may simply failto operate. Various embodiments seek to mitigate such charge lossfailures by reading data from a grouping of memory cells (e.g., in apage of memory cells also containing configuration data or other datafor use by the memory device, or by a host or user of the memorydevice), and responding to a difference, if any, between the number ofread memory cells of that grouping of memory cells having a particulardata state relative to an expected number of memory cells of thatgrouping of memory cells programmed to have the particular data state.

Typical data structures of memory, e.g., of a logical page of memorycells, include storage areas for different types of data. For example,the data structure may include memory cells for storage of user data,e.g., data that is configured to be written to and read from the memoryby a user of the memory, and memory cells for storage of overhead data,e.g., data that is configured to be used internally by the memory and isgenerally unavailable to a user of the memory using a standard readoperation. Overhead data associated with the user data might includedata generated by the memory in response to a write command received bythe memory. For example, overhead data might include status indicators,error correction code data, mapping information and the like. As oneexample, a data structure might contain 16 KB of memory cells in a userdata portion and 2 KB of memory cells in an overhead data portion.Although a memory may be configured to provide limited or no access topre-programmed data, such as data corresponding to configurationparameters, this pre-programmed data may be stored to the memory usingthe same types of data structures (e.g., the same data structures) usedin the memory for storing user data. Typically, only the user dataportion of the data structure is utilized for storing suchpre-programmed data, while the overhead data portion may be unused.

FIGS. 4A-4B illustrate examples of data structures that might be usedwith embodiments. FIG. 4A might represent the data structure of agrouping of memory cells 400A (e.g., a logical page of memory cells,which may also be the physical page of memory cells containing thatlogical page of memory cells) for use with embodiments. The grouping ofmemory cells 400A includes a subset of memory cells 440. The subset ofmemory cells 440 might correspond to a user data portion of a page ofmemory cells. The subset of memory cells 440 may store configurationdata (e.g., for a memory containing the grouping of memory cells 400A),data for use by a user of the memory, and/or data for use by an externaldevice (e.g., a host or other external controller of the memory).Although data stored to the subset of memory cells 440 may be known atthe time of programming data to those memory cells, the memorycontaining the grouping of memory cells 400A would generally have noindication as to the values of that data other than from the memorycells of the subset of memory cells 440 themselves, or from memory cellsof an array of memory cells containing the grouping of memory cells 400Athat were programmed to contain duplicate copies of that data or itscomplement.

The grouping of memory cells 400A further includes a subset of memorycells 442, e.g., that is mutually exclusive from the subset of memorycells 440. The subset of memory cells 442 might correspond to anoverhead data portion of a page of memory cells. Unlike the subset ofmemory cells 440, the subset of memory cells 442 store data having apredetermined (e.g., known) number of memory cells that were programmedto contain a particular data state. Control circuitry of a memorycontaining the grouping of memory cells 400A may be configured to makedecisions responsive to a number of memory cells of the subset of memorycells 442 having the particular data state (e.g., determined in responseto a read operation on the grouping of memory cells 400A) relative tothresholds (e.g., corresponding to numbers of memory cells) that areless than or equal to the predetermined number. The memory cells of thesubset of memory cells 440 and/or the subset of memory cells 442 may beprogrammed as SLC or MLC memory cells.

FIG. 4B might represent the data structure of a grouping of memory cells400B (e.g., a logical page of memory cells, which may also be thephysical page of memory cells containing that logical page of memorycells) for use with embodiments. Although the grouping of memory cells400A depicted one contiguous (e.g., contiguous address space of a pageof memory cells) subset of memory cells 440, the grouping of memorycells 400B includes a plurality of subsets of memory cells 440 ₀-440_(S), which may collectively correspond to the subset of memory cells440. The plurality of subsets of memory cells 440 ₀-440 _(S) mightcorrespond to a user data portion of a page of memory cells. Theplurality of subsets of memory cells 440 ₀-440 _(S) may collectivelystore configuration data (e.g., for a memory containing the grouping ofmemory cells 400B), data for use by a user of the memory, and/or datafor use by an external device (e.g., a host or other external controllerof the memory). Although data stored to the plurality of subsets ofmemory cells 440 ₀-440 _(S) may be known at the time of programming datato those memory cells, the memory containing the grouping of memorycells 400B would generally have no indication as to the values of thatdata other than from the memory cells of the plurality of subsets ofmemory cells 440 ₀-440 _(S) themselves, or from memory cells of an arrayof memory cells containing the grouping of memory cells 400B that wereprogrammed to contain duplicate copies of that data or its complement.

Although the grouping of memory cells 400A depicted one contiguous(e.g., contiguous address space of a page of memory cells) subset ofmemory cells 442, the grouping of memory cells 400B includes a pluralityof subsets of memory cells 442 ₀-442 _(S), which may collectivelycorrespond to the subset of memory cells 442. The plurality of subsetsof memory cells 442 ₀-442 _(S) might correspond to an overhead dataportion of a page of memory cells. Unlike the plurality of subsets ofmemory cells 440 ₀-440 _(S), the plurality of subsets of memory cells442 ₀-442 _(S) store data having a predetermined (e.g., known) number ofmemory cells that were programmed to contain a particular data state.Control circuitry of a memory containing the grouping of memory cells400B may be configured to make decisions responsive to a number ofmemory cells of the plurality of subsets of memory cells 442 ₀-442 _(S)having the particular data state (e.g., determined in response to a readoperation on the grouping of memory cells 400B) relative to thresholds(e.g., corresponding to numbers of memory cells) that are less than orequal to the predetermined number. The memory cells of the plurality ofsubsets of memory cells 440 ₀-440 _(S) and/or the plurality of subsetsof memory cells 442 ₀-442 _(S) may be programmed as SLC or MLC memorycells. Distribution of the data of a subset of memory cells 442 mayprovide better representation of the expected behavior of the data of asubset of memory cells 440.

Although the groupings of memory cells 400A and 400B are each depictedto contain a same number of subsets of memory cells for each type ofdata within their respective grouping (e.g., one for the grouping ofmemory cells 400A, and S+1 for the grouping of memory cells 400B),differing numbers may be used as embodiments described herein are notdependent upon a number of subsets of memory cells for either type ofdata. Similarly, the relative location and/or sizes of individualsubsets of memory cells for the different types of data may be alteredas embodiments described herein are not dependent upon the location of amemory cell for either type of data, and are not dependent upon the sizeof a subset of memory cells for either type of data.

FIGS. 5A-5D depict flowcharts of methods of operating a memory inaccordance with embodiments. In FIG. 5A, at 551, a particular groupingof memory cells is read using a read voltage having a particular voltagelevel. The particular grouping of memory cells might correspond to thememory cells of a data structure of a page of memory cells, e.g., datastructures 400A or 400B of FIG. 4A or 4B, respectively, and a readvoltage level (e.g., a default read voltage level) might be used todetermine whether memory cells of the page of memory cells have theparticular data state. With reference to FIG. 3A as an example, a readvoltage level within the dead space 303 might be used to determinewhether a memory cell has a data state corresponding to the range ofthreshold voltages 302, e.g., a logical ‘0’ data state. With referenceto FIG. 3B as another example, a read voltage level within the labeleddead space 309 might be used to determine whether a memory cell has adata state corresponding to the range of threshold voltages 307, e.g., alogical ‘01’ data state or, if using padding, a logical ‘0’ data state.Although the methods of FIGS. 5A-5D are applicable to the use of SLC orMLC memory cells (with or without the use of padding), the remainingdiscussion of FIGS. 5A-5C will refer to the example of FIG. 3A forsimplicity.

At 553, a number of the memory cells of a subset (e.g., first subset) ofmemory cells of the particular grouping of memory cells having aparticular data state is determined. The first subset of memory cellsmight correspond to those memory cells of the overhead data portion of apage of memory cells having the data structure 400A (e.g., subset ofmemory cells 442) or 400B (e.g., subsets of memory cells 442 ₀-442_(S)), for example. Referring again to the example of FIG. 3A, thenumber of memory cells of the first subset of memory cells having thelogical ‘0’ data state might be determined. Alternatively, a number ofmemory cells of the first subset of memory cells having any data stateother than the particular data state might be determined, which wouldthus determine the number of memory cells having the particular datastate. For some embodiments, each memory cell of the first subset ofmemory cells might be programmed to have the particular data state.

At 555, a decision is made whether the number of memory cells of thefirst subset of memory cells having the particular data state is lessthan a first threshold (e.g., less than a first integer value). If thenumber of memory cells of the first subset of memory cells having theparticular data state is not less than the first threshold, the methodmay end at 557. Alternatively, the method may proceed to point B, andthus to 569 of FIG. 5C to be described infra. The first threshold mightbe equal to the expected number of memory cells of the first subset ofmemory cells that should have the particular data state. This valuemight be equal to the number of memory cells in the first subset ofmemory cells, or it may be less than the number of memory cells in thefirst subset of memory cells. In addition, where the number of memorycells of the first subset of memory cells having the particular datastate is determined by determining the number of memory cells of thefirst subset of memory cells having any data state other than theparticular data state, determining whether the number of memory cells ofthe first subset of memory cells having the particular data state isless than the first threshold might entail determining whether thenumber of memory cells of the first subset of memory cells having anydata state other than the particular data state is greater than or equalto some threshold corresponding to the number (e.g., total number) ofmemory cells of the first subset of memory cells minus an integer value(e.g., the first integer value) corresponding to the first threshold.

If the number of memory cells of the first subset of memory cells havingthe particular data state is less than the first threshold at 555, themethod may proceed to 559, where a decision is made whether the numberof memory cells of the first subset of memory cells having theparticular data state is less than a second threshold (e.g., less than asecond integer value) that is less than the first threshold (e.g., lessthan the first integer value). If the number of memory cells of thefirst subset of memory cells having the particular data state is notless than the second threshold, the method may proceed to 561 to set astatus indicator. The status indicator may be used to provide anindication to an external device, e.g., a host device or other externalcontroller, that data of the memory is deemed to be experiencing somelevel (e.g., minimum level) of errors (e.g., one or more errors)resulting from charge loss. The method may then end at 557, or it mayalternately proceed to point B, and thus to 569 of FIG. 5C. Where thenumber of memory cells of the first subset of memory cells having theparticular data state is determined by determining the number of memorycells of the first subset of memory cells having any data state otherthan the particular data state, determining whether the number of memorycells of the first subset of memory cells having the particular datastate is less than the second threshold might entail determining whetherthe number of memory cells of the first subset of memory cells havingany data state other than the particular data state is greater than orequal to some threshold corresponding to the number (e.g., total number)of memory cells of the first subset of memory cells minus an integervalue (e.g., the second integer value) corresponding to the secondthreshold.

If the number of memory cells of the first subset of memory cells havingthe particular data state is less than the second threshold, the methodmay proceed to 561 to set the status indicator, and may also proceed to563. Although a value of the status indicator may be the same whetherthe number of memory cells of the first subset of memory cells havingthe particular data state is only less than the first threshold, orwhether the number of memory cells of the first subset of memory cellshaving the particular data state is also less than the second threshold,differing values of the status indicator might be used to providedifferent levels of warning regarding the extent to which the data ofthe memory is deemed to be experiencing charge loss errors.

At 563, the voltage level of the read voltage is adjusted in response tothe number of memory cells of the first subset of memory cells havingthe particular data state. In general, decreasing voltage levels of theread voltage would be selected for decreasing numbers of memory cells ofthe first subset of memory cells having the particular data state. Forexample, if the number of memory cells of the first subset of memorycells having the particular data state is less than the secondthreshold, but greater than or equal to a third threshold (e.g., a thirdinteger value), the voltage level of the read voltage might be adjustedto a first adjusted voltage level, e.g., a voltage level less than theparticular (e.g., default) voltage level. If the number of memory cellsof the first subset of memory cells having the particular data state isless than the third threshold, but greater than or equal to a fourththreshold (e.g., a fourth integer value), the voltage level of the readvoltage might be adjusted to a second adjusted voltage level, e.g., avoltage level less than the first adjusted voltage level. If the numberof memory cells of the first subset of memory cells having theparticular data state is less than the fourth threshold, but greaterthan or equal to a fifth threshold (e.g., a fifth integer value), thevoltage level of the read voltage might be adjusted to a third adjustedvoltage level, e.g., a voltage level less than the second adjustedvoltage level. This may be repeated for additional thresholds, selectinga successively lower adjusted voltage level for each threshold. For someembodiments, if the number of memory cells of the first subset of memorycells having the particular data state is less than a particularthreshold, a fail status might be indicated. At 565, the particulargrouping of memory cells is read (e.g., re-read) using the read voltagehaving the adjusted voltage level. The method may optionally proceed topoint B, and thus to 569 of FIG. 5C.

The method described with reference to FIG. 5A may be part of aninitialization routine of a memory. Thus, with reference to FIG. 5B, aninitialization routine of the memory might be started at 567, and thenproceed to point A, and thus 551 of FIG. 5A. An initialization routinemay be performed in response to a reset or power-up of the memory, forexample.

In addition, the method described with reference to FIG. 5A wasdescribed to optionally proceed to point B, and thus to 569 of FIG. 5Cto continue an initialization routine of the memory, where it may bedetermined whether memory cells of a second subset of memory cells ofthe particular grouping of memory cells (e.g., mutually exclusive of thefirsts subset of memory cells) contain valid data. The second subset ofmemory cells might correspond to those memory cells of the user dataportion of a page of memory cells having the data structure 400A (e.g.,subset of memory cells 440) or 400B (e.g., subsets of memory cells 440₀-440 _(S)), for example. This might include using data/data complementpairs and performing an XOR operation as described supra, where thememory cells of the second subset of memory cells might be deemed tocontain valid data if, for each digit or other unit (e.g., byte) of thedata, a valid data/data complement pair is identified, e.g., where aread digit of data of the data/data complement pair has a data state of0 or 1, and its corresponding read digit of data complement of thedata/data complement pair has a data state of 1 or 0, respectively.

At 571, if the memory cells of the second subset of memory cells aredeemed to not contain valid data, the memory may indicate a fail statusat 573 and the initialization routine might end. Note that if copies ofthe data (e.g., data/data complement pairs) of the second subset ofmemory cells are also stored an additional grouping of memory cells(e.g., one or more additional pages of memory cells), the memory may notindicate a fail status at 573 unless no valid copy of the data may beidentified. If the memory cells of the second subset of memory cells aredeemed to contain valid data at 571, the initialization routine maycontinue, e.g., to completion, at 575, and end at 577. Similarly, if theparticular grouping of memory cells is one of a plurality of groupingsof memory cells containing data used by the initialization routine, theinitialization routine may not continue to completion until eachgrouping of memory cells of the plurality of groupings of memory cellshas been processed. For some embodiments, after completion of theinitialization routine, the method might proceed to point C, and thus581 of FIG. 5D.

At 581 of FIG. 5D, the particular grouping of memory cells might be read(e.g., re-read) using the read voltage having the adjusted voltagelevel. The particular grouping of memory cells might then bere-programmed at 583 using the data read from the particular grouping ofmemory cells. This might facilitate restoring lost charge to thosememory cells intended to have the particular data state such that asubsequent read operation using the default read voltage level might bemore successful. Memory cells of the first subset of memory cells mightbe programmed such that each memory cell of the first subset of memorycells intended to have the particular data state might be re-programmedto have the particular data state regardless of whether the read datafor that memory cell indicated the particular data state or another datastate. This could include re-programming each memory cell of the firstsubset of memory cells to have the particular data state regardless oftheir read data states. Because the re-programming can be used torestore lost charge to memory cells indicating a data state lower thantheir intended data state, re-programming can be performed withoutperforming an erase operation on those memory cells prior tore-programming.

While the method of FIG. 5D was shown to follow from completion of aninitialization routine at 575 of FIG. 5C, this method might also beinitiated in response to a command received from an external device,e.g., a host device or other external controller. Similarly, the methodbeginning at 583 might proceed directly from 565 of FIG. 5A. For someembodiments, the method of FIG. 5D might be performed only if theadjusted voltage level corresponds to a particular (e.g., lowest)adjusted voltage level of the method. For example, if the number ofmemory cells of the first subset of memory cells having the particulardata state is greater than or equal to a particular threshold (e.g., athreshold below which might indicate a fail status of the memory), butless than a next higher threshold, re-programming the particulargrouping of memory cells at 583 might be performed, but if the number ofmemory cells of the first subset of memory cells having the particulardata state is greater than or equal to that next higher threshold,re-programming might not be performed.

The particular grouping of memory cells may be one of a plurality ofgroupings of memory cells storing pre-programmed data such asconfiguration data. For example, multiple pages of memory cells might beused to store such data. The methods of FIGS. 5A-5D might be performedfor each of these groupings of memory cells, and each might have arespective adjusted voltage level for the read voltage for that groupingof memory cells, e.g., where the extent of charge loss for one groupingof memory cells differs from the extent of charge loss for anothergrouping of memory cells. Similarly, the first subset of memory cellsmight be programmed to contain more than one programmed data state. Insuch an embodiment, each data state might have a corresponding voltagelevel (e.g., default voltage level) for identifying its correspondingdata state. Similarly, different thresholds, and different levels ofadjusted voltage level for the read voltage, might be used for each datastate.

Values of the thresholds might be determined experimentally, empiricallyor through simulation. For example, a memory could be exposed todifferent temperatures and/or other stresses to mimic an expected usagemodel of an end user. After each stress, the threshold voltagedistribution of the memory cells might be measured and characterized.Such data could then be used to identify thresholds, and theircorresponding adjusted voltage levels, that would be expected to resultin valid data. As an example, adjusted voltage levels might be set tonominal levels, e.g., setting the first adjusted voltage level to be 100mV below the default read voltage level, setting the second adjustedvoltage level to be 100 mV below the first adjusted voltage level,setting the third adjusted voltage level to be 100 mV below the secondadjusted voltage level, etc. The thresholds could then be set based onthe characterization of what levels of shift in the threshold voltagedistribution might produce differing numbers of erroneous indications ofthe particular data state for the first subset of memory cells readusing the default read voltage level. For example, such data could beused to determine what number of erroneous indications of the particulardata state using the default read voltage level would produce a shift(e.g., a largest shift) that could be reliably read using each of theadjusted voltage levels.

FIG. 6 illustrates adjustment of a read voltage level in accordance withan embodiment. The threshold voltage distribution 301 might correspondto the threshold voltage distribution 301 of FIG. 3A. The thresholdvoltage distribution 302 ₀ might correspond to the threshold voltagedistribution 302 of FIG. 3A, e.g., as programmed. The threshold voltagedistribution 302 ₁ might correspond to the threshold voltagedistribution 302 ₀ shifted in response to one level of stress. Thethreshold voltage distribution 302 _(T) might correspond to thethreshold voltage distribution 302 ₀ shifted in response to differentlevel of stress. Fewer or more threshold voltage distributions might becharacterized.

Each of the threshold voltage distributions 302 ₀-302 _(T) might have acorresponding read voltage level expected to reliably read memory cellshaving that threshold voltage distribution. For example, if T=2, theread voltage level L₀ might correspond to the default read voltagelevel, the read voltage level L₁ might correspond to a first adjustedvoltage level, and the read voltage level L_(T) might correspond to asecond adjusted voltage level. In such an example, a first thresholdmight be equal to the number of memory cells expected to have theparticular data state corresponding to the threshold voltagedistribution 302 ₀, a second threshold might be equal to a number ofmemory cells having the threshold voltage distribution 302 ₁ and havingthe particular data state when read using the default read voltage levelL₀, and a third threshold might be equal to a number of memory cellshaving the threshold voltage distribution 302 _(T) and having theparticular data state when read using the default read voltage level L₀.

CONCLUSION

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement that is calculated to achieve the same purpose maybe substituted for the specific embodiments shown. Many adaptations ofthe embodiments will be apparent to those of ordinary skill in the art.Accordingly, this application is intended to cover any adaptations orvariations of the embodiments.

What is claimed is:
 1. A method of operating a memory, comprising:reading a particular grouping of memory cells using a read voltagehaving a particular voltage level; determining a number of memory cellsof a subset of memory cells of the particular grouping of memory cellshaving a particular data state; and if the number of memory cells of thesubset of memory cells having the particular data state is less than aparticular threshold: adjusting a voltage level of the read voltage inresponse to the number of memory cells of the subset of memory cellshaving the particular data state; and reading the particular grouping ofmemory cells using the read voltage having the adjusted voltage level.2. The method of claim 1, wherein the particular threshold is a secondthreshold less than a first threshold, and further comprising: setting astatus indicator of the memory if the number of memory cells of thesubset of memory cells having the particular data state is less than thefirst threshold and greater than or equal to the second threshold. 3.The method of claim 2, wherein setting the status indicator comprisessetting a status indicator indicating that data of the memory is deemedto be experiencing errors resulting from charge loss.
 4. The method ofclaim 2, wherein the first threshold is equal to a number of memorycells of the subset of memory cells expected to have the particular datastate.
 5. The method of claim 1, wherein adjusting the voltage level ofthe read voltage in response to the number of memory cells of the subsetof memory cells having the particular data state comprises: adjustingthe voltage level of the read voltage to a first adjusted voltage levelless than the particular voltage level when the number of memory cellsof the subset of memory cells having the particular data state has afirst value less than the particular threshold; and adjusting thevoltage level of the read voltage to a second adjusted voltage levelless than the first adjusted voltage level when the number of memorycells of the subset of memory cells having the particular data state hasa second value less than the first value.
 6. The method of claim 1,wherein the particular threshold is a first threshold, and whereinadjusting the voltage level of the read voltage in response to thenumber of memory cells of the subset of memory cells having theparticular data state comprises: adjusting the voltage level of the readvoltage to a first adjusted voltage level less than the particularvoltage level if the number of memory cells of the subset of memorycells having the particular data state is less than the first thresholdand greater than or equal to a second threshold that is less than thefirst threshold; and for each value of X=2 through Y, where X and Y areeach integers, and Y is greater than or equal to 2: adjusting thevoltage level of the read voltage to an X^(th) adjusted voltage levelless than an (X−1)^(th) adjusted voltage level if the number of memorycells of the subset of memory cells having the particular data state isless than an X^(th) threshold and greater than or equal to an (X+1)^(th)threshold that is less than the X^(th) threshold.
 7. The method of claim6, further comprising indicating a fail status of the memory if thenumber of memory cells of the subset of memory cells having theparticular data state is less than the (X+1)^(th) threshold when X=Y. 8.The method of claim 6, further comprising re-programming the particulargrouping of memory cells after reading the particular grouping of memorycells using the read voltage having the adjusted voltage level when theadjusted voltage level is the Xth adjusted voltage level when X=Y. 9.The method of claim 8, wherein re-programming the particular grouping ofmemory cells comprises re-programming the memory cells of the subset ofmemory cells to have the particular data state regardless of the datastates of their read data.
 10. The method of claim 1, whereindetermining the number of memory cells of the subset of memory cellshaving the particular data state comprises determining a differencebetween a total number of memory cells of the subset of memory cells anda number of memory cells of the subset of memory cells having athreshold voltage less than a threshold voltage range corresponding tothe particular data state.
 11. The method of claim 10, furthercomprising determining that the number of memory cells of the subset ofmemory cells having the particular data state is less than theparticular threshold by determining that the number of memory cells ofthe subset of memory cells having a threshold voltage less than thethreshold voltage range corresponding to the particular data state isgreater than a total number of memory cells of the subset of memorycells minus an integer value corresponding to the particular threshold.12. The method of claim 1, wherein determining the number of memorycells of the subset of memory cells of the particular grouping of memorycells having the particular data state comprises determining a number ofmemory cells of a contiguous address space of the particular grouping ofmemory cells having the particular data state.
 13. A method of operatinga memory, comprising: reading a particular grouping of memory cellsusing a read voltage having a particular voltage level; determining anumber of memory cells of a subset of memory cells of the particulargrouping of memory cells having a particular data state; and if thenumber of memory cells of the subset of memory cells having theparticular data state is less than a particular threshold that is lessthan or equal to a total number of memory cells of the subset of memorycells: reducing a voltage level of the read voltage in response to thenumber of memory cells of the subset of memory cells having theparticular data state; and reading the particular grouping of memorycells using the read voltage having the reduced voltage level.
 14. Amethod of operating a memory, comprising: reading a particular groupingof memory cells using a read voltage having a particular voltage level;determining a number of memory cells of a subset of memory cells of theparticular grouping of memory cells having any data state of a pluralityof data states other than a highest data state of the plurality of datastates; and if the determined number of memory cells of the subset ofmemory cells is greater than a particular threshold: adjusting a voltagelevel of the read voltage in response to the determined number of memorycells; and reading the particular grouping of memory cells using theread voltage having the adjusted voltage level.
 15. The method of claim14, wherein the particular threshold is a second threshold greater thana first threshold, and further comprising: setting a status indicator ofthe memory if the determined number of memory cells is greater than thefirst threshold and less than or equal to the second threshold.
 16. Themethod of claim 15, wherein setting the status indicator comprisessetting a status indicator indicating that data of the memory is deemedto be experiencing errors resulting from charge loss.
 17. The method ofclaim 15, wherein the first threshold is equal to a number of memorycells of the subset of memory cells expected to have any data state ofthe plurality of data states other than the highest data state of theplurality of data states.
 18. The method of claim 14, wherein adjustingthe voltage level of the read voltage in response to the number ofmemory cells of the subset of memory cells having the particular datastate comprises: adjusting the voltage level of the read voltage to afirst adjusted voltage level less than the particular voltage level ifthe determined number of memory cells is greater than the particularthreshold and less than or equal to a different threshold that isgreater than the particular threshold; and adjusting the voltage levelof the read voltage to a second adjusted voltage level less than thefirst adjusted voltage level if the determined number of memory cells isgreater than the different threshold and less than or equal to anadditional threshold that is greater than the different threshold. 19.The method of claim 14, wherein the particular threshold is a firstthreshold, and wherein adjusting the voltage level of the read voltagein response to the determined number of memory cells comprises:adjusting the voltage level of the read voltage to a first adjustedvoltage level less than the particular voltage level if the determinednumber of memory cells is greater than the first threshold and less thanor equal to a second threshold that is less than the first threshold;and for each value of X=2 through Y, where X and Y are each integers,and Y is greater than or equal to 2: adjusting the voltage level of theread voltage to an X^(th) adjusted voltage level less than an (X−1)^(th)adjusted voltage level if the determined number of memory cells isgreater than an X^(th) threshold and less than or equal to an (X+1)^(th)threshold that is less than the X^(th) threshold.
 20. The method ofclaim 19, further comprising indicating a fail status of the memory ifthe determined number of memory cells is greater than the (X+1)^(th)threshold when X=Y.
 21. The method of claim 19, further comprisingre-programming the particular grouping of memory cells after reading theparticular grouping of memory cells using the read voltage having theadjusted voltage level when the adjusted voltage level is the Xthadjusted voltage level when X=Y.
 22. The method of claim 21, whereinre-programming the particular grouping of memory cells comprisesre-programming the memory cells of the subset of memory cells to havethe highest data state regardless of the data states of their read data.23. The method of claim 14, further comprising reading the particulargrouping of memory cells using the read voltage having the particularvoltage level as part of an initialization routine of the memory, andcontinuing the initialization routine after reading the particulargrouping of memory cells using the read voltage having the adjustedvoltage level.
 24. The method of claim 14, wherein the subset of memorycells comprises a first plurality of subsets of memory cells, andwherein reading the particular grouping of memory cells comprises:reading the particular grouping of memory cells comprising the firstplurality of subsets of memory cells and a second plurality of subsetsof memory cells mutually exclusive of the first plurality of subsets ofmemory cells; wherein, for at least one subset of memory cells of thefirst plurality of subsets of memory cells, that subset of memory cellsof the first plurality of subsets of memory cells is in an address spaceof the particular grouping of memory cells between two adjacent subsetsof memory cells of the second plurality of subsets of memory cells.